1. Field of the Invention
The present invention relates to semiconductor memories and, in more particular, to non-volatile semiconductor memories having NAND type memory cell blocks which are programmable and which may be electrically erased.
2. Description of the Related Art
With the increasing needs for high performance and reliability of digital computer systems, the technique for highly integrated memory cells becomes indispensable. A solid-state memory with enhanced data storage capacity has been demanded strongly, which can replace existing external data storage devices for digital computer systems, such as a magnetic floppy diskette drive unit, a fixed disk unit, or the like.
A presently available electrically erasable programmable read-only memory (to be referred to as an "EEPROM" hereinafter) has technical advantages, such as superior in reliability and higher in data programming rate than the magnetic data storage devices are; however, the total memory amount of the EEPROM is still not so large as to replace the magnetic data storage devices. In the EEPROM, since each of the memory cells is generally constituted by two transistors, it cannot be expected that the integration density increases so as to be high sufficient to enable the EEPROM to have a required amount of memory that permits the EEPROM to substitute for the known magnetic data storage devices.
Recently, a "NAND" type EEPROM has been developed as one of non-volatile semiconductor memories with enchanced data storage capacity. According to the memory of this type, memory cells are grouped into a preselected number of memory cell block sections, each of which includes a plurality of arrays of memory cells, what are called "NAND" cell arrays, or "NAND" cell units. Every one of the memory cells constituting the "NAND" cell unit typically consists of only one transistor of floating gate type, so that only one contact portion is required between every array of memory cells and the corresponding bit line associated therewith. The occupied area of the overall memory cell section on the substrate can thus be reduced to be much smaller than that of a conventional EEPROM, whereby the integration density of the EEPROM can be improved, with the result in the total memory amount being increased.
With the NAND type EEPROM, however, it has been still under development to optimize the circuit configuration of a peripheral drive circuit for NAND cells, which includes row/column decoder circuits and voltage-generation circuits for generating boosted voltages to control data write, erase, and read operations in the NAND memory cell blocks. According to the presently available NAND type EEPROMS, it should be required that each of the memory cell blocks is provided with a peripheral drive circuit having a row decoder associated therewith. This results in that the peripheral circuits occupy much degree of surface area on the substrate of limited size. Increasing in the occupation area of peripheral drive circuits on the substrate acts as a serious bar to efficient use of chip surface area for the memory cell blocks; therefore, it cannot be expected in the NAND type EEPROMs that the total amount of memory is increased as required.